1. Field of the Invention
Embodiments of the present invention relate to a semiconductor memory device which selectively controls a local input/output sense amplifier.
This application claims the priority of Korean Patent Application No. 2003-51119, filed on Jul. 24, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
Semiconductor memory devices which include a plurality of input/output (I/O) buses (e.g. Rambus Dynamic Random Access Memories (RDRAMs)), employ a data line redundancy circuit to repair faults in a memory cell to increase efficiency in column redundancy. Semiconductor memory devices which operate with low power voltage and high operating frequency may include a local input/output sense amplifier. Semiconductor memory devices may have a column matrix structure (in which elements are arranged in columns) to minimize faults due to the high density of elements.
FIG. 1 is a circuit diagram of a semiconductor memory device including a local input/output sense amplifier and a data line redundancy circuit. A semiconductor memory device 100 includes a memory cell array block 110, a redundancy circuit 120, a switch unit SW, and an input/output sense amplifier IOSA. The memory cell array block 110 and the redundancy circuit 120 are located on an array and the switch unit SW and the input/output sense amplifier IOSA are located on a peripheral portion.
The memory cell array block 110 may perform a read operation. A row address is first applied to the memory cell array block 110 to enable a word line WL and a bit line sense amplifier BLSA amplifies a charge stored in a cell capacitor. If a read command and a column address are applied to the memory cell array block 110, a column select line CSL is enabled and data amplified in a bit line BL and an inverted bit line BLB is transmitted to a local input/output sense amplifier LSA. If a local input/output sense amplifier enable signal PLIOSE is applied to the local input/output sense amplifier LSA, the data is amplified once more and loaded on a global input/output line GIO and an inverted global input/output line GIOB.
The data loaded on the pair of global input/output lines GIO and GIOB is amplified to a complementary metal oxide semiconductor (CMOS) level at a terminal end of the pair of global input/output lines GIO and GIOB by the input/output sense amplifier IOSA. The data is then forwarded to a pipe line (not shown) and transmitted to the outside of the memory cell array block 110 through a series of pipe lines (not shown), an output driver (not shown), and a DQ pin. The switch unit SW selectively outputs data loaded on the pair of global input/output lines GIO and GIOB in response to a first select signal SEL1 or data loaded on a pair of redundancy global input/output lines RGIO and RGIOB in response to a second select signal SEL2.
A read operation of the redundancy circuit 120 is similar to the memory cell array block 110. The redundancy circuit 120 includes a redundancy cell RCELL1, a redundancy bit line RBL, an inverted redundancy bit line RBLB, a redundancy bit line sense amplifier RBLSA, a redundancy local input/output line RLIO, an inverted redundancy local input/output line RLIOB, a redundancy local input/output sense amplifier RLSA, the redundancy global input/output line RGIO, and the inverted redundancy global input/output line RGIOB. The switch unit SW selects one path between the pair of global input/output lines GIO and GIOB and the pair of redundancy global input/output lines RGIO and RGIOB.
FIG. 2 is a circuit diagram of a redundancy circuit in the semiconductor memory device of FIG. 1. If a redundancy column select line RCSL is enabled, data amplified by a redundancy word line RWL and a redundancy bit line sense amplifier RBLSA is transmitted to a redundancy local input/output line RLIO and an inverted redundancy local input/output line RLIOB. The data is then amplified by a local input/output line sense amplifier RLSA. The data is then loaded on a redundancy global input/output line RGIO and an inverted redundancy global input/output line RGIOB. If a second select signal SEL2 is enabled and a first select signal SEL1 is disabled, the data loaded on the pair of redundancy global input/output line RGIO and RGIOB is applied to an input/output sense amplifier IOSA.
A local input/output sense amplifier enable signal PLIOSE includes column address strobe (CAS) command read information and block code information. PLIOSE is connected to a memory cell array block 210, such that the local input/output sense amplifier enable signal PLIOSE can enable both a local input/output sense amplifier LSA (of the memory cell array block 210) and the redundancy local input/output sense amplifier RLSA (of a redundancy circuit 220). Accordingly, when the redundancy circuit 220 performs a sensing function, the local input/output sense amplifier LSA of the memory cell array block 210 performs a dummy sensing function, which causes unnecessary current consumption.
FIG. 3 is a circuit diagram of a local input/output line sense amplifier of FIGS. 1 and 2. If data of a high level is loaded on a local input/output line LIO and data of a low level is loaded on an inverted local input/output line LIOB, then a third transistor TR3 is turned on and a fourth transistor TR4 is turned off.
If a local input/output line sense amplifier enable signal PLIOSE is applied at a high level, then first, second, and fifth transistors TR1, TR2, and TR5 are turned on. As a result, a global input/output line GIO increases to a high level and an inverted global input/output line GIOB decreases to a low level. Since the local input/output line sense amplifier LSA and a redundancy local input/output line sense amplifier RLSA have the same structure, both the local input/output line sense amplifier LSA and the redundancy local input/output line sense amplifier RLSA are turned on if the local input/output line sense amplifier enable signal PLIOSE is enabled.
FIG. 4 is a circuit diagram of a memory cell array block and a redundancy circuit of a semiconductor memory device which has a column matrix structure. A cell, a word line, a pair of bit lines, and a pair of local input/output lines are not shown for simplification. A memory cell array block is divided into an upper memory cell array block 410 and a lower memory cell array block 430. The upper memory cell array block 410 includes a global input/output line GIO, an inverted global input/output line GIOB, and an upper local input/output line sense amplifier LSAU for reading data. The lower memory cell array block 430 includes a lower local input/output line sense amplifier LSAL, an input/output line IO, and an inverted input/output line IOB.
An inverted circuit is divided into an upper redundancy circuit 420 and a lower redundancy circuit 440. The pair of input/output lines IO and IOB of the lower memory cell array block 430 are used as a default path through which data sensed by the upper memory cell array block 410, the upper redundancy circuit 420, and the lower redundancy circuit 440 is applied to an input/output sense amplifier IOSA.
To use the pair of input/output lines IO and IOB of the lower memory cell array block 430 as the default path, a switch unit SW is required for selecting one of the pair of global input/output lines GIO and GIOB, a pair of upper redundancy global input/output lines RGIOU and RGIOBU, and a pair of lower redundancy global input/output lines RGIOL and RGIOBL.
FIG. 5 is a circuit diagram of a lower redundancy circuit in a semiconductor memory device of FIG. 4. To connect a lower redundancy circuit 540 to a pair of input/output lines IO and IOB, a first select signal SEL1 and a second upper select signal SELU2 are disabled and a second lower select signal SELL2 is enabled.
If a lower sense amplifier enable signal PLIOSE_L is applied, a lower redundancy local input/output line sense amplifier RLSAL is enabled to perform a sensing function. At the same time, a lower local input/output line sense amplifier LSAL of a lower memory cell array block 530 is also enabled and performs a dummy sensing function. Accordingly, both data sensed by the lower redundancy local input/output line sense amplifier RLSAL and invalid data dummy sensed by the lower local input/output line sense amplifier LSAL are disadvantageously loaded on the pair of input/output lines IO and IOB.
FIG. 6A is a graph illustrating a waveform of a pair of input/output lines when a lower redundancy circuit of FIG. 4 performs a sensing function. FIG. 6B is a graph illustrating a waveform of a pair of input/output lines when a local input/output line sense amplifier of a lower memory cell array block of FIG. 4 performs a dummy sensing function. FIG. 6C is a graph illustrating a waveform of a pair of input/output lines when a lower redundancy circuit and a lower local input/output line sense amplifier of a lower memory cell array block of FIG. 4 operate together.
Referring to FIG. 6C, when the lower local input/output line sense amplifier performs the dummy sensing function operates together with the lower redundancy circuit, a voltage level of a pair of input/output lines IO and IOB decreases, as compared with the graph of FIG. 6A. This causes a decrease in the voltage level input to an input/output line sense amplifier IOSA, reducing sensing speed of the input/output line sense amplifier IOSA.